Nvidia's RTX Spark, the Windows version of its GB10-powered mini PC, contains a neural processing unit that Nvidia has barely acknowledged exists. According to a week-long investigation by XDA Developers, that NPU is a real, physically separate chip with its own registers, clock domain and power rail, not a software trick to satisfy Microsoft's Copilot+ certification checklist.
The RTX Spark runs the same GB10 silicon Nvidia already sells in the Linux-based DGX Spark, just under Windows. German outlet ComputerBase reported at an Nvidia event in San Francisco that the NPU is a 55 TOPS accelerator meant solely for Copilot+ features, the Microsoft-defined bar for on-device AI tasks like Windows Studio Effects and Recall. Beyond that disclosure and a single block diagram, Nvidia has published almost nothing about the part, and third-party software can't reach it through normal interfaces even though Windows lists it in Task Manager and Device Manager.
Tracing a chip Nvidia won't talk about
The XDA reporter dug through firmware, Nvidia's drivers and its developer tools on an HP OmniBook Ultra 16 built around the same GB10 platform, and concluded the hardware is a descendant of Nvidia's Deep Learning Accelerator, or DLA, architecture, built around RISC-V cores. HP's ACPI tables define a device called DLA0 with two memory-mapped register windows, 256 KiB at one address and 64 KiB at another, sitting on the SoC die alongside the display, camera and audio blocks. The GPU, by contrast, lives on a separate die connected over Nvidia's chip-to-chip link. HP's firmware even includes a "DLA Support" toggle and logic for hiding the NPU from Windows entirely.
Running nvidia-smi on the machine shows the NPU counted as a second GPU, identifying itself with the architecture name "NPU3" and a UUID that starts with "DLA-." It idles at 430 MHz and climbs to 1,562 MHz on its own independent clock, reporting separate power draw from the GPU. Windows treats it as a distinct class of hardware too, routing it through MCDM, the compute-only driver model meant for accelerators without a display output, rather than treating it as a GPU with extra steps.
Getting it to actually compute something
Proving the chip existed in silicon required getting a real workload to run on it rather than quietly handing the job to the GPU. Nvidia's retail driver ships with cuDLA, the same API used for its Jetson embedded accelerators, and the RTX Spark reports hardware version 2, the generation found in Jetson Orin chips. Standalone execution on the NPU kept failing, so every task had to be routed through a CUDA stream on the GPU in what Nvidia calls hybrid mode.
Building a compiled network for the chip meant using TensorRT 11.4, which restores DLA support only for Windows on Arm, in beta, and specifically excludes Jetson, DriveOS and Linux SBSA devices, a category that includes the DGX Spark. That detail matters: GB10's firmware appears to reference a DLA block that Linux simply can't see, leaving open whether the DGX Spark's hardware is missing or just switched off.
Once running, the reporter got a full ResNet-50 image classification network executing correctly on the NPU in both FP16 and INT8, the latter a mode Nvidia's own documentation says the platform doesn't support. Oddly, INT8 ran no faster than FP16, which is part of what makes the chip's purpose so unclear even after a week of digging through it.
Nvidia has not published an official explanation for why the NPU is this restricted or whether broader access is coming once TensorRT's DLA support exits beta.
CDFiled by The Computing Desk
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